Electronic systems such as computer systems continue to be designed to meet two goals that are occasionally at odds, those goals being decreased cost and decreased power consumption. These goals are driven by the continuing trends of ever increasing varieties of uses being found for such devices, including increasing uses requiring ever greater portability, and the ever present desire to make such devices more accessible to more end users through decreases in costs. Requirements for increased portability have placed demands on such electronic systems to be smaller, lighter and capable of operating for increasingly longer periods of time off of portable power sources such as batteries. Requirements for decreased costs have placed demands on such electronic systems to be made from smaller numbers of more highly integrated components to reduce parts stocking and assembly costs.
Reducing the physical size of the memory system in such electronic systems by finding ways to reduce the quantity of memory devices making up the memory system would seem, at first, to be a way of achieving both goals. Reducing the number of memory devices can be a way to reduce overall power consumption by the memory system, and can result in a memory system that is physically smaller. One way to achieve such a reduction in the number of memory devices is the employment of a unified memory architecture (UMA) in which both a graphics controller and a processor of an electronic system share the same memory devices such that the same memory system serves as both graphics and system memory. Depending on the graphics and processing capabilities, as well as the memory requirements of a given electronic system, implementing UMA could literally cut the total number of memory devices in a given electronic system in half, resulting in considerable power, weight and space reductions.
In the vast majority of current day electronic systems, both system and graphics memory tend to be made up of dynamic random access memory (DRAM) devices which, as those skilled in the art will readily recognize, require refresh operations to be carried out on every memory cell being used to store data at regular intervals in order to preserve that data. During normal operation of a memory system employing DRAM memory devices, refresh operations are interleaved at regular intervals with normal read/write operations. In trying to conserve power, many current day DRAM memory devices provide a lower power mode referred to as “self-refresh” mode in which the buses and interfaces to the DRAM memory devices are powered down, and the DRAM memory devices consume only enough power to carry out refresh operations, internally, and retain data. With the buses and interfaces to the DRAM memory devices powered down, normal read/write operations cannot be carried out. In other words, in self-refresh mode, data is retained, but cannot be accessed.
Many current day electronic systems implement a form of lower power mode in which DRAM memory devices serving as system memory devices are placed in self-refresh mode, while DRAM memory devices serving as graphics memory devices continue to be operated normally to accommodate the need to support refreshing an image provided on a display device driven by a graphics controller. As those familiar with graphics systems will readily recognize, the majority of types of display devices used in current day electronic systems require retransmission of image data to a display device at regular intervals to refresh the display to maintain an image on the display. This regular retransmission of an image requires the image data to be read out of graphics memory at regular intervals, and therefore, if it is desired to maintain an image on the display of an electronic system, the buses and interfaces to graphics memory cannot be powered down.
In current day electronic systems in which entirely separate buses, interfaces and memory devices are used to serve as system and graphics memory, it is easily possible to power down system memory while leaving graphics memory undisturbed. However, where UMA is implemented, causing the same memory devices of a unified memory system to serve both system and graphics memory functions, problems arise in attempting to power down system memory while leaving graphics memory undisturbed.